Fundamentally, a computer bus consists of a set of parallel “wires” attached to several connectors into which peripheral boards may be plugged.

Typically the processor is connected at one end of these wires. Memory may also be attached via the bus. The wires are split into several functional groups such as:

Address: Specifies the peripheral and register within the peripheral that is being accessed.

Data: The information being transferred to or from the peripheral.

Control: Signals that effect the data transfer operation. It is the control signals and how they are manipulated that embody the bus protocol.

Beyond basic data transfer, busses typically incorporate advanced features such as:

Interrupts

DMA

Power distribution

Additional control lines manage these features. The classic concept of a bus is a set of boards plugged into a passive backplan.

But there are also many bus implementations based on cables interconnecting stand-alone boxes. The GPIB (general purpose interface bus) is a classic example. Contemporary examples of cable busses include USB (universal serial bus) and IEEE-1394 (trademarked by Apple Computer under the name Firewire™). Nor is the backplane restricted to being passive as illustrated by the typical PC motherboard implementation.

Bus Taxonomy

Computer busses can be characterized along a number of dimensions. Architecturally, busses can characterized along two binary dimensions: synchronous vs. asynchronous and multiplexed vs. non-multiplexed. In a synchronous bus, all operations occur on a specified edge of a master clock signal. In asynchronous busses operations occur on specified edges of control signals without regard to a master clock. Early busses tended to be asynchronous. Contemporary busses are generally synchronous.

A bus can be either multiplexed or non-multiplexed. In a multiplexed bus data and address share the same signal lines. Control signals identify when the common lines contain address information and when they contain data. A non-multiplexed bus has separate wires for address and data.

The basic advantage of a multiplexed bus is fewer wires which in turn means fewer pins on each connector, fewer high-power driver circuits and so on. The disadvantage is that it requires two phases to carry out a single data transfer — first the address must be sent, then the data transferred. Contemporary busses are about evenly split between multiplexed and non-multiplexed.

Busses can be characterized in terms of the number of bits of address and data. Contemporary busses are typically either 32 or 64 bits wide for both address and data. Not surprisingly, multiplexed busses tend to have the same number of address and data bits.

Address width 8, 16, 32, 64

Data width 1, 8, 16, 32, 64

Transfer rate 1 MHz up to several hundred MHz

Maximum length Several centimeters to several meters

Number of devices A few up to many

A key element of any bus protocol is performance. How fast can it transfer data? Early busses were limited to a few megahertz, which closely matched processor performance of the era. The problem in contemporary systems is that the processor is often many times faster than the bus and so the bus becomes a performance bottleneck. Bus length is related to transfer speed. Early busses with transfer rates of one or two megahertz allowed maximum lengths of several meters. But with higher transfer rates comes shorter lengths so that propagation delay doesn’t adversely impact performance.

The maximum number of devices that can be connected to a bus is likewise restricted by high performance considerations. Early busses could tolerate high-power, relatively slow driver circuits and could thus support a large number of attached devices. High performance busses such as PCI limit driver power and so are severely restricted in terms of number of devices.